Do not waste another second tracking where BANKSEL or PAGESEL instructions are required to prevent incorrect addressing. Simply write your code, assemble it, and let the Opt tool do the rest. The Opt tool will insert and remove banking and paging instructions to ensure that every address is pointing to the correct memory location with a minimum of switching overhead.
No need to search through your code for subroutines that are no longer used. The Opt tool will find and eliminate them for you. But it goes much further and also uses its simulation engine to find branches that are never taken and data tables that are never read.
The problem with optimized code is keeping the timing critical code intact. Our recommendation is to run Opt without timing constraints to find the best code. Then insert the timing start and stop markers into the comments of your assembly code to get a report of all timing variations. Adjust the timing to your liking and use the untouchable markers in your comments to prevent optimization from changing the timing.
The output from this tool is a new listing file and a .hex file ready to program into your chip.
Since this software is an extension to the Scan tool expect the first demo soon after Scan tool v1.0 is released. The official release of the Opt tool is planned for the spring of 2007.
The free trial is a full version of the Scan Tool running on our servers. Submit your code and the results will return by email.
We are nearing the official release of Scan Tool v1.0. You can still get the pre release for half price and enjoy a year of free updates including v1.0.
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